Progressive scaling of the feature sizes and critical dimensions of semiconductor devices has advanced the performance and increased the functional capability and device density of integrated circuits formed in and on semiconductor substrates or wafers. Back end of line (BEOL) interconnect structures have been developed that complement advances in device density by more effectively routing signal paths between the constituent semiconductor devices. Circuit performance may eventually be limited by the signal-transmission effectiveness and efficiency of the interconnect structure.
Back end of line operations are performed on the semiconductor substrate in the course of device manufacturing following first metallization. In a multilevel metallization network or scheme, the interconnect structure usually employs two or more separate levels of conductive lines that extend laterally across the substrate. Insulating layers of dielectric material separate and electrically isolate the different conductive line levels. Adjacent levels of conductive lines are connected by conductive contacts extending through dielectric material separating those adjacent levels.
The conductive lines and the contacts that connect conductive lines in different levels operate to distribute signals among the devices and integrated circuits on the substrate. Ordinarily, the conductive lines of the first metallization, which are in the initial level closest to the substrate, primarily interconnect the devices of the integrated circuit and may provide circuit-to-circuit connections. The conductive lines in the upper levels complete the circuit-to-circuit connections and make contact with input and output terminals coupled with a support such as a module, substrate or card.
The signal propagation delay of the interconnect structure depends upon the resistance of the interconnect lines and contacts and upon the overall capacitance of the dielectric materials in which the conductive lines and contacts are embedded. The resistance contribution to the signal propagation delay may be reduced by using copper (Cu) as the constituent conductor for the conductive lines and contacts. The capacitance contribution to the signal propagation delay may be reduced by using low dielectric constant (k) dielectrics having a dielectric constant, k, of about 3.9 or less. In particular, the combination of copper metal and low-k dielectric materials has been found to minimize signal propagation delay particularly well as feature sizes and critical dimensions are scaled below 90 nm.
Copper-dielectric BEOL interconnect structures are routinely fabricated by damascene processes that rely on standard lithographic and dry etch techniques. In single damascene processes, vias are selectively etched in a dielectric layer masked by a patterned resist. After the resist is stripped, the vias are filled with metal to establish contacts with underlying conductor lines or other conductive structures. Trenches are then etched in another patterned layer of dielectric material deposited on the initial dielectric layer and subsequently filled with metal to define overlying conductor lines. The overlying and underlying conductive lines are electrically coupled by the contacts in the vias. Dual-damascene processes differ in that the trenches and vias are etched in one or more layers of insulating or dielectric material and then filled simultaneously by a single blanket deposition of metal. Repeating these damascene processes forms subsequent levels of the interconnect structure.
Conventional copper-dielectric interconnect structures include a conductive liner situated between the dielectric material and the conductive lines and contacts. In particular, the use of copper metal in interconnect manufacture requires an adhesion layer between the copper metal and the dielectric material to promote bonding and a diffusion barrier between the copper metal and the dielectric material to isolate the copper from the dielectric material. Conventionally, a bilayer liner of TaN/Ta may be deposited on the dielectric material bordering the vias and the trenches. The TaN/Ta bilayer liner has proven to be a reliable barrier for copper interconnects that isolates the conductive copper metal from the low-k dielectric material as well as adhering firmly to the conductive metal and the dielectric material. After the vias and the trenches are lined with the TaN/Ta bilayer liner, a copper seed layer is deposited for facilitating the ensuing copper plating process that forms copper contacts in the via and trench features.
As the critical dimensions of interconnect structures continue to scale downwardly, the thickness of both the liner and copper seed layers must likewise scale to maintain circuit performance. If the liner and copper seed layers are kept at a fixed dimension, the interconnect layers themselves will shrink disproportionately to the critical dimension. Integrated circuit performance would suffer because of an increased signal propagation delay. Moreover, top pinch-off may eventually occur in the narrowed vias and trenches during the subsequent copper plating process, which has the potential to trap an unfilled void within the bulk of the deposited copper.
During the metallization process, various antecedent steps are employed to ensure high yield and reliability of the interconnect structure. One such step is a directional non-selective sputter etch preclean, often performed using argon ions, that removes native copper oxide, and other possible contaminants, from the copper line exposed at the via bottom. This sputter etch preclean has a tendency to breach the liner at the via and trench bottoms and, subsequently, etch the conductor and/or dielectric material of the underlying interconnect level. Conductive materials like copper, which have a high sputter yield, are then susceptible to erosion by sputter etching. Diffusion of metals like copper into the dielectric material may compromise the integrity of the dielectric materials in the insulating layers isolating the levels of the interconnect structure. Metal contamination of the dielectric material may result in leakage currents among the interconnect layers.
To alleviate the effect of sputtered metal, an initial barrier layer of the liner may be deposited on the sidewalls and bottom of the vias and trenches of the overlying level in the interconnect structure before performing the sputter etch preclean. The barrier layer intervenes between the dielectric material and the sputtered copper that deposits on the via sidewalls, trench sidewalls, and trench bottom. The sputter etch preclean may gouge out or roughen sections of the underlying interconnect level exposed at the via bottoms. Subsequently-deposited layers of the liner cannot adequately repair the physical damage without resorting to a layer thickness that fails to scale with the critical dimensions of interconnect structures. Because of the roughening, the subsequently-deposited layers of the liner are not deposited in a conformal manner on the dielectric material. The thickness-limited result may be a discontinuous liner, which may permit diffusion of sputtered and re-deposited metal into the dielectric material bordering the vias and trenches in the overlying level of the interconnect structure.
What is needed, therefore, are design structures including improved interconnect structures that mitigate the discontinuities in via and trench liners produced by the sputter etch preclean process.